IDT82V3202NLG【PDF 29/117 页】IC PLL WAN EBU SGL 68-VFQFPN

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IDT82V3202

EBU WAN PLL

Functional Description

September 11, 2009

3.3

INPUT CLOCKS & FRAME SYNC SIGNALS

Altogether two clocks and two frame sync signals are input to the

device.

3.3.1

INPUT CLOCKS

The device provides two CMOS input clock ports: IN1_CMOS and

IN2_CMOS.

According to the input clock source, the following clock sources are

supported:

T1: Recovered clock from STM-N or OC-n

T2: PDH network synchronization timing

T3: External synchronization reference timing

The clock sources can be from T1, T2 or T3.

For SDH and SONET networks, the default frequency is different.

SONET / SDH frequency selection is controlled by the IN_SONET_SDH

bit. During reset, the default value of the IN_SONET_SDH bit is deter-

mined by the SONET/SDH pin: high for SONET and low for SDH. After

reset, the input signal on the SONET/SDH pin takes no effect.

3.3.2

FRAME SYNC INPUT SIGNALS

Two 2 kHz, 4 kHz or 8 kHz frame sync signals are input on the

EX_SYNC1 and EX_SYNC2 pins respectively. They are CMOS inputs.

The input frequency should match the setting in the SYNC_FREQ[1:0]

bits. The frame sync signals are only valid for the OC-n clock (6.48 MHz,

19.44 MHz, 38.88 MHz and 77.76 MHz) input.

Only one of the two frame sync input signals is used for frame sync

output signal synchronization. Refer to Chapter 3.13.2 Frame SYNC

Output Signal for details.

Table 3: Related Bit / Register in Chapter 3.3

Bit

Register

Address (Hex)

IN_SONET_SDH

INPUT_MODE_CNFG

SYNC_FREQ[1:0]

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